1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, and more particularly relates to a semiconductor memory device having an ECC (Error Correction Code) circuit incorporated therein and a control method of the semiconductor memory device.
2. Description of Related Art
In a semiconductor memory device having an ECC circuit incorporated therein, such as an ECC-circuit built-in DRAM, there is a necessity to store an “information bit” actually required and a “check bit” used for correcting the information bit when an error occurs in the information bit. Thus, during a write operation, the information bit is written and coded to generate the check bit (a coding step). During a read operation, the information bit and the check bit are read, the read information bit is coded (a coding step), and the coded information bit is compared to the check bit. In this way, a defective part in the information bit is found (a check step), the defective part in the information bit is corrected, and then the resultant bit is outputted (correction). As described above, “coding” is performed in the write operation and “coding”→“check”→“correction” is performed in the read operation.
The number of check bits required for correcting a certain bits of information bits is calculated by information theory. Even in the simplest single error correction, the number of check bits m capable of correcting k bits of information bits needs to satisfy the formula (15) mentioned below. When the number of bits to be corrected is increased, more check bits are required accordingly.2m≧m+k+1  (15)
From the formula (15), when k is 8, m becomes 4, when k is 16, m becomes 5, and when k is 32, m becomes 6. As the number of information bits is increased, the ratio of number of check bits m required to the number of information bits k is decreased. However, as the DRAM requires a “byte mask function” for masking a part of data to be read/written at the same time, the check bit has to be assigned per one byte, that is, 8 bits even if a large number of bits of data are read/written at the same time. In this case, for 8 bits of information bits, 4 bits of check bits are required. The total number of bits is thus 12 bits, which is 1.5 times larger than the information bit. This means that a memory cell array becomes 1.5 times larger, resulting in a significant increase in chip size.
To avoid this problem, during a read operation, read is performed as usual like “coding”→“check”→“correction”. Meanwhile, during a write operation, read (“coding”→“check”→“correction”) is performed first, the corrected data is mixed with write data, and write (“coding”) is then performed using updated total information bit. Before write is actually performed upon the memory cell array, already written data is read temporarily, so that the number of information bits is increased.
The method described in Japanese Patent Application Laid-open (JP-A) No. 2007-42176 is known to be one of methods utilizing the above principle. The method described in JP-A No. 2007-42176 utilizes a sense-amplifier activating operation and a pre-charge operation in a DRAM. “Coding”→“check”→“correction” (corresponding to the read operation described above) is performed first by an ACT command and the corrected data is held at a sense amplifier. When a READ command is inputted, the corrected data held by the sense amplifier is read. When a write command is inputted, write data is overwritten on the corrected, data held by the sense amplifier. “Coding” (corresponding to the write operation described above) is finally performed by a pre-charge command.
That is, in the read command, the data corrected and read by the ACT command is read. In the write command, the data read by the ACT command is mixed with the write data and the resultant data is coded finally by the pre-charge command, so that the write operation is performed. According to JP-A No. 2007-42176, already written data is read temporarily using the row cycle, thereby increasing the number of information bits. The ECC operation is thus performed without any limitation on the number of information bits.